View AD8004AR-14_8594972.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev. c a ad8004 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ?2003 analog devices, inc. all rights reserved. quad 3000 v/ s, 35 mw current feedback amplifier features high speed 250 mhz ? db bandwidth (g = +1) 3000 v/ s slew rate 21 ns settling time to 0.1% 1.8 ns rise time for 2 v step low power 3.5 ma/amp power supply current (35 mw/amp) single supply operation fully specified for +5 v supply good video specifications (r l = 150 , g = +2) gain flatness 0.1 db to 30 mhz 0.04% differential gain error 0.10 differential phase error low distortion ?8 dbc thd at 5 mhz ?1 dbc thd at 20 mhz high output current of 50 ma available in a 14-lead pdip, soic, and cerdip applications image scanners active filters video switchers special effects general description t he ad8004 is a quad, low power, high speed amplifier designed to operate on single or dual supplies. it utilizes a current feed- back architecture and features high slew rate of 3000 v/ m s mak ing the ad8004 ideal for handling large amplitude pulses. additionally, the ad8004 provides gain flatness of 0.1 db to frequency ?mhz 1 ? ? 1 500 10 40 100 ? ? ? 0 ? ? ? ? normalized frequency response ?db normalized flatness ?db 0.1 0 ?.1 ?.2 ?.3 ?.4 ?.5 5v s +5v s +5v s 5v s g = +2 v in = 50mv rms r l = 100 r f = 1.10k r package figure 1. frequency response and flatness, g = +2 connection diagram pdip (n), cerdip (q), and soic (r) packages 14 13 12 11 10 9 8 1 2 3 4 7 6 5 1 23 4 ad8004 ( top view) output ?n +in +v s +in ?n output ? s +in ?n output output ?n +in 30 mhz while offering differential gain and phase error of 0.04% and 0.10 . this makes the ad8004 suitable for video electronics such as cameras and video switchers. the ad8004 offers low power of 3.5 ma/amplifier and can run on a single +4 v to +12 v power supply, while being capable of delivering up to 50 ma of load current. all this is offered in a small 14-lead dip or 14-lead soic package. these features make this amplifier ideal for portable and battery powered appli- cations w here size and power are critical. the outstanding bandwidth of 250 mhz along with 3000 v/ m s of slew rate make the ad8004 useful in many general-purpose, high speed applications where dual power supplies of up to 6v and single supplies from 4 v to 12 v are needed. the ad8004 is available in the industrial temperature range of 40 c to +85 c in the n and r packages, and in the military temperature range of ?5 c to +125 c in the q package. 0.04 0.03 0.02 0.01 0.00 ?.01 ?.02 ?.03 ?.04 1 st diff gain ?% 0.12 0.10 0.08 0.06 0.04 0.02 0.00 ?.02 ?.04 diff phase ?degrees 2 nd 3 rd 4 th 5 th 6 th 7 th 8 th 9 th 10 th 11 th 1 st 2 nd 3 rd 4 th 5 th 6 th 7 th 8 th 9 th 10 th 11 th 80 ire r l = 150 v s = 5v r f = 1.21k 80 ire r l = 150 v s = 5v r f = 1.21k figure 2. differential gain/differential phase
important links for the ad8004 * last content update 08/18/2013 01:36 am parametric selection tables find similar products by operating parameters high speed amplifiers selection table documentation an-692: universal precision op amp evaluation board an-649: using the analog devices active filter design tool an-356: user's guide to applying and measuring operational amplifier specifications mt-057: high speed current feedback op amps mt-051: current feedback op amp noise considerations mt-034: current feedback (cfb) op amps mt-059: compensating for the effects of input capacitance on vfb and cfb op amps used in current-to-voltage converters a stress-free method for choosing high-speed op amps ug-111: universal evaluation board for quad, high speed op amps offered in 14-lead soic packages adi warns against misuse of cots integrated circuits current feedback amplifiers part 1: ask the applications engineer-22 current feedback amplifiers part 2: ask the applications engineer-23 two-stage current-feedback amplifier space qualified parts list design tools, models, drivers & software analog filter wizard 2.0 ad8004a spice macro-model evaluation kits & symbols & footprints view the evaluation boards and kits page for documentation and purchasing symbols and footprints design collaboration community collaborate online with the adi support team and other designers about select adi products. follow us on twitter: www.twitter.com/adi_news like us on facebook: www.facebook.com/analogdevicesinc design support submit your support request here: linear and data converters embedded processing and dsp telephone our customer interaction centers toll free: americas: 1-800-262-5643 europe: 00800-266-822-82 china: 4006-100-006 india: 1800-419-0108 russia: 8-800-555-45-90 quality and reliability lead(pb)-free data sample & buy ad8004 view price & packaging request evaluation board request samples check inventory & purchase find local distributors * this page was dynamically generated by analog devices, inc. and inserted into this data sheet. note: dynamic changes to the content on this page (labeled 'important links') does not constitute a change to the revision number of the product data sheet. this content may be frequently modified. powered by tcpdf (www.tcpdf.org)
rev. c ? ad8004?pecifications ad8004a ad8004s parameter conditions min typ max min typ max unit dynamic performance ? db bandwidth, n package g = +2, r f = 698 ? 185 mhz g = +1 , r f = 806 ? 250 mhz bandwidth for 0.1 db flatness g = +2 30 30 mhz slew rate g = +2, v o = 4 v step 3000 3000 v/ s g = ?, v o = 4 v step 2000 2000 v/ s settling time to 0.1% g = +2, v o = 2 v step 21 21 ns rise and fall time (10% to 90%) g = +2, v o = 2 v step 1.8 1.8 ns noise/harmonic performance total harmonic distortion f c = 5 mhz, v o = 2 v p-p, r l = 1 k ? ?8 ?8 dbc crosstalk, r package, worst case f = 5 mhz, g = +2, r l = 1 k ? ?9 db crosstalk, n package, worst case f = 5 mhz, g = +2, r l = 1 k ? ?4 db input voltage noise f = 10 khz 1.5 1.5 nv/ hz input current noise f = 10 khz, +in 38 38 pa/ hz ?n 38 38 pa/ hz differential gain error ntsc, g = +2, r l = 150 ? , r f = 1.21 k ? 0.04 0.04 % differential phase error ntsc, g = +2, r l = 150 ? , r f = 1.21 k ? 0.10 0.10 degree differential gain error ntsc, g = +2, r l = 1 k ? , r f = 1.21 k ? 0.01 0.01 % differential phase error ntsc, g = +2, r l = 1 k ? , r f = 1.21 k ? 0.04 0.04 degree dc performance input offset voltage 1.0 3.5 1.0 3.5 mv t min to t max 1.5 5 1.5 6 mv offset drift 15 15 v/ c ?nput bias current 35 90 35 90 a t min to t max 110 120 a +input bias current 40 110 40 110 a t min to t max 120 130 a open-loop transresistance v o = 2.5 v 170 290 170 290 k ? t min to t max 220 220 k ? input characteristics input resistance +input 2 2 m ? ?nput 50 50 ? input capacitance +input 1.5 1.5 pf input common-mode voltage range 3.2 3.2 v common-mode rejection ratio offset voltage v cm = 2.5 v 52 58 52 58 db ?nput current v cm = 2.5 v, t min to t max 11 a/v +input current v cm = 2.5 v, t min to t max 12 12 a/v output characteristics output voltage swing r l = 150 ? 3.9 3.9 v output current 50 50 ma short circuit current 100 180 100 180 ma power supply operating range 2.0 6.0 2.0 6.0 v total quiescent current 14 17 14 17 ma t min to t max 16 20 16 23 ma power supply rejection ratio ? v s = 2 v 56 62 5 662 db ?nput current t min to t max 0.5 0.5 a/v +input current t min to t max 44 a/v specifications subject to change without notice. (@ t a = +25 c, v s = 5 v, r l = 100 , unless otherwise noted.)
rev. c 3 ad8004 ad8004a ad8004s parameter conditions min typ max min typ max unit dynamic performance ? db bandwidth, n package g = +2, r f = 698 ? 150 mhz g = +1, r f = 806 ? 200 mhz bandwidth for 0.1 db flatness g = +2 30 30 mhz slew rate g = +2, v o = 2 v step 1100 1100 v/ s settling time to 0.1% g = +2, v o = 2 v step 24 24 ns rise and fall time (10% to 90%) g = +2, v o = 2 v step 2.3 2.3 ns noise/harmonic performance total harmonic distortion f c = 5 mhz, v o = 2 v p-p, r l = 1 k ? ?5 ?5 dbc crosstalk, r package, worst case f = 5 mhz, g = +2, r l = 1 k ? ?9 db crosstalk, n package, worst case f = 5 mhz, g = +2, r l = 1 k ? ?4 db input voltage noise f = 10 khz 1.5 1.5 nv/ hz input current noise f = 10 khz, +in 38 38 pa/ hz ?n 38 38 pa/ hz differential gain error ntsc, g = +2, r l = 150 ? , r f = 1.21 k ? 0.06 0.06 % differential phase error ntsc, g = +2, r l = 150 ? , r f = 1.21 k ? 0.25 0.25 degree differential gain error ntsc, g = +2, r l = 1 k ? , r f = 1.21 k ? 0.01 0.01 % differential phase error ntsc, g = +2, r l = 1 k ? , r f = 1.21 k ? 0.08 0.08 degree dc performance input offset voltage 1.0 2.5 1.0 2.5 mv t min to t max 13 14mv offset drift 15 15 v/ c ?nput bias current 20 80 20 80 a t min to t max 100 110 a +input bias current 35 100 35 100 a t min to t max 115 125 a open loop transresistance v o = +1.5 v to +3.5 v 140 230 140 230 k ? t min to t max 170 170 k ? input characteristics input resistance +input 2 2 m ? ?nput 50 50 ? input capacitance +input 1.5 1.5 pf input common-mode voltage range 3.2 3.2 v common-mode rejection ratio offset voltage v cm =+1vto+3v 5 257 525 7db ?nput current v cm = +1 v to +3 v, t min to t max 22 a/v +input current v cm = +1 v to +3 v, t min to t max 15 15 a/v output characteristics output voltage swing r l = 150 ? 0.9 to 4.1 0.9 to 4.1 v output current 50 50 ma short circuit current 95 95 ma power supply operating range 0, +4 +12 0, +4 +12 v total quiescent current 13 14 13 14 ma t min to t max 14.5 15.5 14.5 17.5 ma power supply rejection ratio ? v s = +1 v, v cm = +2.5 v 56 62 56 62 db ?nput current t min to t max 11 a/v +input current t min to t max 66 a/v specifications subject to change without notice. specifications (@ t a = +25 c, v s = +5 v, r l = 100 , unless otherwise noted.)
rev. c ad8004 ? absolute maximum ratings 1 supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6 v internal power dissipation . . . . . . . . . . . . . . . . . . . . . note 2 input voltage (common mode) . . . . . . . . . . . . . . . . . . . . v s differential input voltage . . . . . . . . . . . . . . . . . . . . . . . 2.5 v output short circuit duration . . . . . . . . . . . . . . . . . . . . . . observe power derating curves storage temperature range (n, q, r) . . . . ?5 c to +125 c operating temperature range a grade . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?0 c to +85 c s grade . . . . . . . . . . . . . . . . . . . . . . . . . . . ?5 c to +125 c lead temperature range (soldering 10 sec) . . . . . . . . +300 c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 specification is for device in free air: 14-lead pdip package: ja = 90 c/w, jc = 30 c/w 14-lead soic package: ja = 140 c/w, jc = 30 c/w 14-lead cerdip package: ja = 110 c/w, jc = 30 c/w ordering guide temperature package package model range description option ad8004an 40 c to +85 c 14-lead pdip n-14 AD8004AR-14 40 c to +85 c 14-lead soic r-14 AD8004AR-14-reel 40 c to +85 c 13" tape and reel r-14 AD8004AR-14-reel7 40 c to +85 c 7" tape and reel r-14 ad8004sq 55 c to +125 c 14-lead cerdip q-14 maximum power dissipation the maximum power that can be safely dissipated by the ad8004 is limited by the associated rise in junction temperature. the maximum safe junction temperature for plastic en capsu- lated devices is determined by the glass transition temperature of the plastic, approximately +150 c. exceeding this limit temporarily m ay cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. exceeding a junction temperature of +175 c for an extended period can result in device failure. while the ad8004 is internally short circuit protected, this may not be sufficient to guarantee that the maximum junction tem- perature is not exceeded under all conditions. to ensure proper operation, it is necessary to observe the maximum power ratings. 61.9 0.1 f 0.1 f 10 f 10 f 499 249 v in +v s ? s 50 scope input 50 figure 4. test circuit; gain = ? caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad8004 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. 0.1 f 0.1 f 10 f 10 f 604 604 50 v in +v s ? s 50 scope input 50 figure 3. test circuit; gain = ?
rev. c ad8004 ? tpc 4.* 100 mv step response; g = ?, v s = 2.5 v or 5 v tpc 5.* step response; g = ?, v s = 5 v frequency ?mhz 1 normalized frequency response ?db ? ? 1 500 10 40 100 ? ? ? 0 ? ? ? ? g = ? g = ? g = ?0 v s = 5v r f = 499 v in = 50mv rms r l = 100 n package tpc 6. frequency response; g = ?, ?, ?0 tpc 1.* 100 mv step response; g = +2, v s = 2.5 v or 5 v tpc 2.* step response; g = +2, v s = 5 v frequency ?mhz 2 ? ? 1 500 10 normalized frequency response ?db 40 100 ? ? 0 1 ? ? ? ? g = +2, r f = 604 g = +10, r f = 499 r l = 100 v in = 50mv (g = +1, +2) v in = 5mv (g = +10) g = +1, r f = 698 tpc 3. frequency response; g = +1, +2, +10; v s = 5 v * v s = 2.5 v operation is identical to v s = +5 v single-supply operation. t ypical performance characteristics
rev. c ad8004 ? frequency ?mhz 9 ? ?1 1 500 10 output level ?dbv 40 100 ? 0 3 6 ? ?2 ?5 ?8 1v rms g = +2 v s = 5v r f = 604 tpc 7. large signal frequency response; v s = 5.0 v, g = +2, r f = 604 ? frequency ?mhz ?0 ?00 120 distortion ?dbc 10 ?0 ?0 ?0 ?0 ?0 g = +2 v o = 2v p-p r f = 698 2nd r l = 150 3rd r l = 150 2nd r l = 1k 3rd r l = 1k tpc 8. distortion vs. frequency; v s = 5 v frequency ?mhz 1 ? ? 1 500 10 40 100 ? ? ? 0 ? ? ? ? normalized frequency response ?db normalized flatness ?db 0.1 0 ?.1 ?.2 ?.3 ?.4 ?.5 g = +2 v in = 50mv rms r l = 100 r f = 1.10k r package 5v s +5v s +5v s 5v s tpc 9. frequency response and flatness, g = +2 frequency ?mhz 3 ?2 ?7 1 500 10 40 100 ? ? ? 0 ?5 ?8 ?1 ?4 1v rms output level ?dbv g = +2 v s = +5v r f = 604 tpc 10. large signal frequency response; v s = +5.0 v, g = +2, r f = 604 ? frequency ?mhz ?0 ?0 ?00 120 distortion ?dbc 10 ?0 ?0 ?0 ?0 g = +2 v o = 2v p-p r f = 698 2nd r l = 150 3rd r l = 150 2nd r l = 1k 3rd r l = 1k tpc 11. distortion vs. frequency; v s = +5 v cmrr ?db 604 604 50 v out 154 154 57.6 v in frequency ?mhz ?0 ?5 ?0 0.1 500 110 100 ?0 ?5 ?0 ?5 ?0 ?5 ?0 ?5 +5v s 5v s +5v s 5v s 0.03 tpc 12. cmrr vs. frequency; v s = 5 v or +5 v, v in = 200 mv rms, other sides are equal, rto
rev. c ad8004 ? input current noise ? p a/ hz 10 100 1k 10k 100k 1m frequency ?hz 1000 500 200 100 300 10 1 70 50 40 30 20 + or ?input current noise voltage noise input voltage noise ?nv/ hz 100 10 tpc 13. noise vs. frequency, v s = +5 v or 5 v s frequency ?mhz 1 0.1 500 1 impedance ? 10 100 10 100 0.1 0.01 0.03 +5v s 5v s r bt = 50 5v s or +5v s r bt = 0 g = +2 r f = 698 power = 0dbm (224mv rms) tpc 14. output impedance vs. frequency frequency ?mhz ?80 0.1 500 110 100 90 0 ?40 ?60 0.03 60 50 40 30 20 10 phase ?degrees 0 ?0 gain ?db v in = ?0dbm v s = 5v gain phase tpc 15. open-loop voltage gain and phase psrr ?db frequency ?hz 0 ?0 10k 500m 100k 1m 10m ?0 ?0 ?0 ?0 ?0 ?0 ?0 100m +psrr ?srr g = +2 5v s or 2.5v s r f = 1k 100mv rms on top of dc bias tpc 16. psrr vs. frequency frequency ?mhz crosstalk ?db ?0 ?0 ?20 0.1 500 110 100 ?0 ?0 ?0 ?0 ?0 ?0 ?00 ?10 0.03 output = side 2 output = side 4 output = side 3 g = +2 r f = 1.10k 5v s v in = 200mv rms input to side 1 r l1 = 1k r package tpc 17. crosstalk (output to output) vs. frequency frequency ?hz gain ?db 110 60 10 1m 1g 10m 100m 70 80 90 100 50 40 30 20 100k phase gain 0 ?0 ?00 ?50 ?00 phase ?degrees tpc 18. open-loop transimpedance gain
rev. c ad8004 ? tpc 19. short-term settling time tpc 20. long-term settling time 0.04 0.03 0.02 0.01 0.00 ?.01 ?.02 ?.03 ?.04 1 st diff gain ?% 0.12 0.10 0.08 0.06 0.04 0.02 0.00 ?.02 ?.04 diff phase ?degrees 2 nd 3 rd 4 th 5 th 6 th 7 th 8 th 9 th 10 th 11 th 80 ire r l = 150 v s = 5v r f = 1.21k 80 ire r l = 150 v s = 5v r f = 1.21k 1 st 2 nd 3 rd 4 th 5 th 6 th 7 th 8 th 9 th 10 th 11 th tpc 21. differential gain/differential phase 9 8 7 6 5 3 2 10 100 1000 10000 load resistance ? 4 1 0 swing ?v p-p +5v s 5v s g = +2 r f = 1.21k tpc 22. output voltage swing vs. load 9 8 7 6 5 4 3 2 1 0 r l = 100 r l = 1k total supply voltage ?v g = +2 r f = 1.21k f = 100khz 10 3456789101112 peak-to-peak output at clipping point ?v tpc 23. output swing vs. supply 0.03 0.02 0.01 0.00 ?.01 ?.02 ?.03 diff gain ?% diff phase ?degrees 80 ire r l = 1k v s = 5v r f = 1.21k 0.04 0.03 0.02 0.01 0.00 ?.01 ?.02 ?.03 ?.04 1 st 2 nd 3 rd 4 th 5 th 6 th 7 th 8 th 9 th 10 th 11 th 1 st 2 nd 3 rd 4 th 5 th 6 th 7 th 8 th 9 th 10 th 11 th 80 ire r l = 1k v s = 5v r f = 1.21k tpc 24. differential gain/phase, r l = 1 k ?
rev. c ad8004 ? theory of operation the ad8004 is a member of a new family of high speed current- feedback (cf) amplifiers offering new levels of bandwidth, distortion, and signal-swing capability vs. power. its wide dynamic range capabilities are due to both a complementary high speed bipolar process and a new design architecture. the ad8004 is basically a two stage (figure 30) rather than the conventional one stage design. both stages feature the current-on-demand property associated with current feedback amplifiers. this gives an unprecedented ratio of quiescent current to dynamic performance. the im portant properties of slew rate and full pow er bandwidth benefit from this performance. in addition the sec ond gain stage buffers the effects of load impedance, significantly reducing distortion. a full discussion of this new amplifier architecture is available on the data sheet for the ad8011. this discussion only covers the basic principles of operation. dc and ac characteristics as with traditional op amp circuits the dc closed-loop gain is defined as: a v = g = 1 + r f r n noninverting operation a v = g =? r f r n inverting operation the more exact relationships that take into account open-loop gain errors are: a v = g 1 + 1 ? g a o ( s ) + r f t o ( s ) for inverting (g is negative) a v = g 1 + g a o ( s ) + r f t o ( s ) for noninverting (g is posi tive) in these equations the open-loop voltage gain (a o (s)) is common to both voltage and current-feedback amplifiers and is the ratio of output voltage to differential input voltage. the open-loop transimpedance gain (t o (s)) is the ratio of output voltage to inverting input current and is applicable to current-feedback amplifiers. the open-loop voltage gain and open-loop transim- pedance gain (t o (s)) of the ad8004 are plotted vs. frequency in tpcs 15 and 18. these plots and the basic relationships can be used to predict the first order performance of the ad 8004 over frequency. at low closed-loop gains the term (r f /t o (s)) dominates the frequency response characteristics. this gives the result that bandwidth is constant with gain, a familiar property of current feedback amplifiers. an r f of 1 k has been chosen as the nominal value to give optimum frequency response with acceptable peaking at gains of +2/?. as can be seen from the above relationships, at higher closed- loop gains reducing r f has the e ffect of increasing closed- loop bandwidth. table i gives optimum values for r f and r g for a variety of gains. v p q1 q2 ipp ipn inp ipn v n z i iq1 q3 q4 ie c p 1 c p 1 a2 c l r g r f v o c d icq + io v o iq1 ad8004 a2 c p 2 c d a3 r l a1 a1 z2 figure 5. simplified block diagram
rev. c ad8004 ?0 driving capacitive loads the ad8004 was designed primarily to drive nonreactive loads. if driving loads with a capacitive component is desired, best settling response is obtained by the addition of a small series resistance as shown in figure 6. the accompanying graph shows the optimum value for r series vs. capacitive load. it is worth noting that the frequency response of the circuit when driving large capacitive loads will be dominated by the passive roll-off of r series and c l . 1k r l 1k c l ad8004 r series 1k figure 6. driving capacitive load 40 30 20 010152025 c l ?pf 10 r series ? 5 figure 7. recommended r series vs. capacitive load for 30 ns settling to 0.1% optimizing flatness the fine scale gain flatness and ? db bandwidth is affected by r feedback selection as is normal of current feedback amplifiers. with the exception of gain = +1, the ad8004 can be adjusted for either maximal flatness with modest closed-loop bandwidth or for mildly peaked-up frequency response with much more bandwidth. figure 8 shows the effect of three evenly spaced r f changes upon gain = +1 and gain = +2. table i shows the recommended component values for achieving maximally flat frequency response as well as a faster slightly peaked-up fre- quency response. printed circuit board parasitics and device lead frame parasitics also control fine scale gain flatness. the ad8004r package, because of its small lead frame, offers superior parasitics relative to the n package. in the printed circuit board environment, parasitics such as extra capacitance caused by two parallel and vertical flat conductors on opposite pc board sides in the region of the summing junction will cause some bandwidth extension and/or increased peaking. in noninverting gains, the effect of extra capacitance on summing junctions is far more pronounced than with inverting gains. figure 9 shows an example of this. note that only 1 pf of added junction capacitance causes about a 70% bandwidth extension and additional peaking on a gain = +2. for an inverting gain = ?, 5 pf of additional summing junction capacitance caused a small 10% bandwidth extension. extra output capacitive loading also causes bandwidth exten- sions and peaking. the effect is more pronounced with less resistive loading from the next stage. figure 10 shows the effect of direct output capacitive loads for gains of +2 and ?. for both gains c load was set to 10 pf or 0 pf (no extra capacitive l oading). for each of the four traces in figure 10 the resistive loads were 100 . figure 11 also shows capacitive loading effects w ith a lighter output resistive load. note that even though bandwidth is extended 2 , the flatness dramatically suffers. frequency ?mhz ? 1 500 10 40 100 1 0 ? v in = 50mv rms v s = 5v r l = 100 r package ? ? ? normalized gain ?db, g = +2 2 ? 0 1 ? ? ? ? ? r f = 1.10k r f = 604 g = +1 g = +2 ? ? gain ?db, g = +1 r f = 845 r f = 909 r f = 1.1k r f = 698 figure 8. r feedback vs. frequency response, g = +1/+2 frequency ?mhz 2 ? 1 500 10 40 100 ? 0 ? ? v in = 50mv rms r l = 100 5v s ?0 ?2 ?4 normalized gain ?db, g = ? normalized gain ?db, g = +2 2 ? ? 0 ? ? ?0 ?2 ?4 c j = 1pf c j = 0 c j = 5.1pf c j = 0 g = +2 g = ? figure 9. frequency response vs. added summing junction capacitance
rev. c ad8004 ?1 frequency ?mhz 2 ? 1 500 10 40 100 ? 0 ? ? v in = 50mv 5v s r l = 100 ?0 ?2 ?4 normalized gain ?db, g = ? normalized gain ?db , g = +2 2 ? ? 0 ? ? ?0 ?2 ?4 c l = 10pf c l = 0 c l = 10pf c l = 0 g = +2, r f = 1.10k g = ?, r f = 698 figure 10. frequency response vs. capacitive loading, r l = 100 ? output frequency ?mhz 2 ? 1 500 10 40 100 ? 0 ? ? ?0 ?2 ?4 normalized gain ?db, g = 2 c l = 10pf c l = 0 g = +2 r l = 1k 5v s v in = 50mv rms r f = 1.2k figure 11. flatness with 10 pf capacitive load driving a single-supply a/d converter new cmos a/d converters are placing greater demands on the amplifiers that drive them. higher resolutions, faster conversion rates, and input switching irregularities require superior settling characteristics. in addition, these devices run off a single +5 v supply and consume little power, so good single-supply operation with low power consumption is very important. the ad8004 is well positioned for driving this new class of a/d converters. figure 12 shows a circuit that uses an ad8004 to drive an ad876, a single supply, 10-bit, 20 msps a/d converter that requires only 140 mw. using the ad8004 for level shifting and driving, the a/d exhibits no degradation in performance com- pared to when it is driven from a signal generator. the analog input of the ad876 spans 2 v centered at about 2.6 v. the resistor network and bias voltages provide the level shifting and gain required to convert the 0 v to 1 v input signal to a 3.6 v to 1.6 v range that the ad876 wants to see. biasing the noninverting input of the ad8004 at 1.6 v dc forces the inverting input to be at 1.6 v dc for linear operation of the amplifier. when the input is at 0 v, there is 3.2 ma flowing out of the summing junction via r1 (1.6 v/499 ? ). r3 has a current of 1.2 ma flowing into the summing junction (3.6 v ?1.6 v)/ 1.65 k ? . the difference of these two currents (2 ma) must flow through r2. this current flows toward the summing junction and requires that the output be 2 v higher than the summing junction or at 3.6 v. when the input is at 1 v, there is 1.2 ma flowing into the sum- ming junction through r3 and 1.2 ma flowing out through r1. these currents balance and leave no current to flow through r2. thus the output is at the same potential as the inverting input or 1.6 v. the input of the ad876 has a series mosfet switch that turns on and off at the sampling rate. this mosfet is connected to a hold capacitor internal to the device. the on impedance of the mosfet is about 50 ? , while the hold capacitor is about 5 pf. in a worst case condition, the input voltage to the ad876 will change by a full-scale value (2 v) in one sampling cycle. when the input mosfet turns on, the output of the op amp will be connected to the charged hold capacitor through the series resistance of the mosfet. without any other series resistance, the instantaneous current that flows would be 40 ma. this would cause settling problems for the op amp. the series 100 ? resistor limits the current that flows instanta- neously after the mosfet turns on to about 13 ma. this resistor cannot be made too large or the high frequency perfor- mance will be affected. the sampling mosfet of the ad876 is closed for only half of each cycle or for 25 ns. approximately seven time constants are required for settling to 10 bits. the series 100 ? resistor along with the 50 ? on resistance and the hold capacitor, create a 750 ps time constant. these values leave a comfortable margin for settling. obtaining the same results with the op amp a/d combination as compared to driving with a signal generator indicates that the op amp is settling fast enough. overall the ad8004 provides adequate buffering for the ad876 a/d converter without introducing distortion greater than that of the a/d converter by itself. 3.6v 1.6v +5v 10 f r2 1k r3 1.65k r1 499k 3.6v v in 50 0.1 f 1.6v 1v 0v 100 +1.6v +3.6v reft refb 0.1 f 0.1 f 1/4 ad8004 ad876 figure 12. ad8004 driving the ad876 layout considerations the specified high speed performance of the ad8004 requires careful attention to board layout and component selection. table i shows the recommended component values for the ad8004 and figures 14?6 show the layout for the ad8004 eval uation boards (14-lead dip and soic). proper r f design techniques and low parasitic component selection are mandatory.
rev. c ad8004 ?2 table i. recommended component values 1 and typical bandwidths alternate alternate alternate alternate gain ?0 ? ? ? ? +1 +1 +2 +2 +10 ad8004 (dip) package type r f ( ? ) 499 698 499 649 499 1.21 k 806 1.10 k 698 499 r g ( ? ) 49.9 348 249 649 499 1.10 k 698 54.9 r t 2 ( ? ) none 57.6 61.9 53.6 54.9 50 50 50 50 50 small signal bw @ 5 v s ( mhz) 155 125 180 135 190 150 250 115 185 135 peaking @ 5 v s < 0.3 db none 0.3 db none 0.3 db 1.3 db 1.7 db < 0.14 db 0.4 db < 0.3 db 0.1 db flatness @ 5 v s ( mhz) 25 30 35 small signal bw @ +5 v s ( mhz) 135 105 155 120 160 130 200 95 150 120 ad8004 (soic) package type r f ( ? ) 499 698 499 750 499 1.10 k 698 1.10 k 604 499 r g ( ? ) 49.9 348 249 750 499 1.10 k 604 54.9 r t 2 ( ? ) none 57.6 61.9 53.6 54.9 50 50 50 50 50 small signal bw @ 5 v s ( mhz) 155 130 190 125 195 150 225 110 175 135 peaking @ 5 v s < 0.7 db < 0.1 db 0.5 db none 0.4 db 1.3 db 1.8 db < 0.1 db 0.5 db < 0.2 db 0.1 db flatness @ 5 v s ( mhz) 35 25 30 small signal bw @ +5 v s ( mhz) 135 115 175 110 165 130 195 95 155 120 notes 1 resistor values listed are standard 1% tolerance. 2 r t chosen for 50 ? characteristic input impedance. the pcb should have a ground plane covering all unused portions of the component side of the board to provide a low impedance ground path. the ground plane should be removed from the area near the input pins to reduce stray capacitance. chip capacitors should be used for supply bypassing (see figure 13). one end should be connected to the ground plane and the other within 1/8" of each power pin. an additional (4.7 f to 10 f) tantalum electrolytic capacitor should be connected in parallel. the feedback resistor should be located close to the inverting input pin in order to keep the stray capacitance at this node to a minimum. capacitance greater than 1 pf at the inverting input will significantly affect high speed performance when operating at low noninverting gains. an example of extra inverting input capacitance can be seen on the plot of figure 10. stripline design techniques should be used for long signal traces (greater than about 1"). these should be designed with the proper system characteristic impedance and be properly termi- nated at each end. noninverting configuration c1 0.1 f c2 0.1 f c4 10 f c3 10 f r t v in v out +v s ? s r g r f r bt , 50 1/4 c1 0.1 f c2 0.1 f c4 10 f c3 10 f r t v in v out +v s ? s r g r f r bt , 50 1/4 inverting configuration figure 13. inverting and noninverting configurations
rev. c ad8004 ?3 figure 14. evaluation board silkscreen (top)
rev. c ad8004 ?4 figure 15 evaluation board layout (top side) figure 16. evaluation board layout (bottom side, looking through the board)
rev. c ad8004 ?5 outline dimensions 14-lead plastic dual in-line package [pdip] (n-14) dimensions shown in inches and (millimeters) 14 1 7 8 0.685 (17.40) 0.665 (16.89) 0.645 (16.38) 0.295 (7.49) 0.285 (7.24) 0.275 (6.99) 0.100 (2.54) bsc seating plane 0.180 (4.57) max 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.150 (3.81) 0.130 (3.30) 0.110 (2.79) 0.060 (1.52) 0.050 (1.27) 0.045 (1.14) 0.150 (3.81) 0.135 (3.43) 0.120 (3.05) 0.015 (0.38) 0.010 (0.25) 0.008 (0.20) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.015 (0.38) min controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design compliant to jedec standards mo-095-ab 14-lead standard small outline package [soic] (r-14) dimensions shown in millimeters and (inches) controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design coplanarity 0.10 14 8 7 1 6.20 (0.2441) 5.80 (0.2283) 4.00 (0.1575) 3.80 (0.1496) 8.75 (0.3445) 8.55 (0.3366) 1.27 (0.0500) bsc seating plane 0.25 (0.0098) 0.10 (0.0039) 0.51 (0.0201) 0.33 (0.0130) 1.75 (0.0689) 1.35 (0.0531) 8 0 0.50 (0.0197) 0.25 (0.0098) 45 1.27 (0.0500) 0.40 (0.0157) 0.25 (0.0098) 0.19 (0.0075) compliant to jedec standards ms-012ab 14-lead ceramic dual in-line package [cerdip] (q-14) dimensions shown in inches and (millimeters) 14 17 8 0.310 (7.87) 0.220 (5.59) pin 1 0.005 (0.13) min 0.098 (2.49) max 0.100 (2.54) bsc 15 0 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20) seating plane 0.200 (5.08) max 0.785 (19.94) max 0.150 (3.81) min 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.070 (1.78) 0.030 (0.76) 0.060 (1.52) 0.015 (0.38) controlling dimensions are in inches; millimeters dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design
rev. c ?6 c01045??/03(c) printed in u.s.a. ad8004 revision history location page 3/03?ata sheet changed from rev. b to rev. c. updated format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . universal added cerdip (q) package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 added text to general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 changes to specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 changes to absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 changes to ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 edited maximum power dissipation section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 deleted figure 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 edited y axis of tpc 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 edited optimizing flatness section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 edits to figure 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 changes to table i . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 updated outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

▲Up To Search▲

Price & Availability of AD8004AR-14

	To Download AD8004AR-14 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .